In ARM Processors, ARM is an acronym used for Advanced RISC Machines as these are a family member of those CPUs which are based on RISC architecture. More simply, Advanced RISC machines have created the architecture of ARM processors thus called so.
These processors offer architectural simplicity due to which it exists in small size, is less complex, and thereby offers high performance when implemented within a system.
Content: ARM Processor
Introduction to ARM
ARM came into existence in the year 1983 and was developed by Acorn Computers. It has achieved tremendous popularity as it was the first commercial RISC implementation. However, in the year 1990, it was owned by Acorn, Apple, and VLSI. ARM processors are considered to be rigid but these are very much performance-oriented.
The ARM processor is a 32 bit that offers single cycle execution of instructions with high clock speed. Due to the features possessed, it is considered to be a fundamental component of embedded systems. The major reason behind the success of ARM is its simple and powerful design that has undergone constant technical upgrades after invention. Due to the simplicity of the processors, these show utility in portable devices such as smartphones, tablets, networking modules, advanced music players, etc.
Features of ARM Processors
We have already discussed in the beginning that ARM processors are based on RISC architecture. Thus, it includes key features of the RISC architecture, which are as follows:
1. Instructions: A single instruction is of 32 bit. This allows fetching of every instruction in one cycle thereby making the operations simple. Here each instruction is of fixed length thereby permitting the future instructions to get fetched while the previous ones are in getting executed. While this facility is not provided by CISC architecture as in that case, the instructions exhibit variable size whose execution requires multiple cycles. This means ARM processors offer simple instruction decoding.
2. Registers: The RISC machines contain large uniform register files. It has 37 registers of 32 bits each out of which only 16 can be used at a time. Unlike CISC processors where each register is dedicated for specific purposes, in RISC, any register can contain either data or address. This increases the execution process of the whole system.
3. Pipelining: It is based on 3 stage pipelining, which provides maximum throughput. Basically, in this case, by the time the first instruction is executing, the next one will be decoded, and next to next one will be fetched. This allows fetching, decode and execution to occur simultaneously. This means that on each cycle there is the advancement of one step that saves time and hence for execution microcodes are not required for instruction execution like CISC processors.
4. Load/Store Model: In this architecture, all operations take place within the register. Through load/store operation, data from the memory is loaded into the register and over that data, the operation is performed. Once the operation gets done then the result of the same is stored in the memory. This means, unlike CISC, which supports data processing on memory directly, it does not provide memory-based operations.
ARM Instruction Sets
The various instructions are as follows:
Whenever a branch i.e., B instruction is encountered during an ongoing execution then the processor immediately switches to the provided address location and begins to execute the operation from that location. This instruction permits forward and backward branches up to 32 MB.
Data Processing instructions
The various data processing instructions occur within the general-purpose registers. These instructions include:
1. Arithmetic and logic instructions: These are used to perform various arithmetic and logic operations. Here two source operands are used and the output of the operation is stored within the destination register. The results of arithmetic and logic instructions can be directly written into the Program Counter as it is a general-purpose register.
2. Comparison instructions: The comparison instructions have the same format as that of arithmetic and logic instructions. With this instruction, the operation takes place on two operands but rather than storing the results in registers, the contents of flag registers get updated.
3. Multiply instructions: According to the length of the bits after multiplication, this is divided into two classes, namely,
- 32-bit result: It is a normal result and all 32 bits of the result get stored within a register.
- 64-bit result: It is considered to be a long result and to store the 64 bit, two separate registers are required.
4. Count leading zero instruction: Through this instruction, the device counts for the total number of zeros from MSB to LSB in the given sequence. The count obtained gets stored in a register.
Load and Store instructions
These instructions are as follows:
1. Load and Store register: Through load register instruction, 8-bit, 16-bit, or 32-bit can be loaded into the register from the memory. While store register instruction transfers the data from the register to memory.
2. Load and Store multiple registers: This instruction permits loading and storing multiple general-purpose registers in block form to or from the memory. Thus, the supportable addressing modes are pre-increment, post-increment, pre-decrement, post-decrement.
3. Swap register and memory content: The swap (SWP) instruction works sequentially in a way that it allows:
- Loading a value from a memory location that is given in the register.
- Further, whatever, content is present within the register is stored in the same memory location.
- Moreover, the value loaded into the memory is also loaded into the register.
Thus, by keeping the register the same for the above two steps, the data existing inside the register and memory location gets interchanged.
Status register transfer instruction
This instruction allows transferring the content of the current program status register to or from a general-purpose register. This involves the following steps:
- Setting the value of the condition code flag.
- Setting the interrupt enable bits.
- Lastly, setting the mode of the processor.
The coprocessor instructions involve:
1. Data processing instructions: This instruction is responsible for internal operations that are specifically registered for the co-processor.
2. Register transfer instructions: With this instruction, the data of the co-processor is transferred to or from the register.
3. Data transfer instructions: By using this instruction, the data of the co-processor is transferred to or from the memory, and the address of which is calculated by the processor.
Exception generating instructions
In order to give rise to specific exceptions, the following instructions are used:
1. Software interrupts instruction: Through SWI instruction, software interrupts exception occurs. With this instruction, one demands OS-based service and by this the device switches to privileged processor mode. By doing so, an unfavorable operation accesses a favorable one in the manner which the operating system allows.
2. Software breakpoint instruction: Through BKPT instruction, an abort exception is generated. In the presence of debugger software, abort exception is treated as a breakpoint. While when there is debug hardware then abort exception does not occur and BKPT instruction is directly considered as a breakpoint.
Applications of ARM Processor
It has various commercial applications such as in modern mobile phones, digital television, set-top boxes, hard drives, inkjet printers, GPS navigation systems, etc. Not only these, it is useful in portable gaming units, camcorders, AirPods, routers, etc.