**Definition**: Encoders (or binary encoders) are the combinational circuits that are used to change the applied input signal into a coded format at the output. These digital circuits come under the category of **medium scale integrated** circuit.

Basically, these are used to minimize the number of data lines as well as to code the input data.

In binary encoders among all the input lines, only a single input line gets activated at a time. And the logic circuitry present inside the encoder converts this active signal into coded binary format.

Suppose for an encoder the number of input lines is 2^{n} then the output lines will be n.

Thus **less number of data lines** are required by encoded data to get transmitted from an end to another.

## 4:2 Binary Encoder

As we have recently discussed the relation between input and output data lines. So, let us understand how a 4:2 binary encoder operates.

The figure below represents 4:2 binary encoder:

Here 4 input lines are present and for 4 input lines, by the relation 2^{n}, the number of output must be 2. Hence it is said to be 4:2 encoder, because of having 4 input lines and 2 output lines.

Let us see the operation of 4:2 binary encoder in detail.

We know in case 4 of input lines the applied input bits will be 00, 01, 10, 11 denoting the input lines I_{0}, I_{1}, I_{2}, I_{3}. As we have already mentioned that at a time only a single input gets activated. So, that activated input will be generated at the output of the encoder.

The figure shown below will provide you with a better idea about the operation performed by 4:2 encoder:

Suppose here I_{1} input line is activated then, at the output Y_{0} line will hold 0 and Y_{1} will hold 1. As I1 denotes 01 binary value.

The **truth table** of 4:2 binary encoder is given below:

I_{0} | I_{1} | I_{2} | I_{3} | Y_{0} | Y_{1} |
---|---|---|---|---|---|

0 | 0 | 0 | 1 | 0 | 0 |

0 | 0 | 1 | 0 | 0 | 1 |

0 | 1 | 0 | 0 | 1 | 0 |

1 | 0 | 0 | 0 | 1 | 1 |

Also, the logic circuit involved in 4:2 binary encoder is shown below:

This circuit represents the logic circuitry behind the operation performed by 4:2 binary encoder.

## Types of Encoders

Encoders are classified into 4 categories:

- Decimal to BCD Encoder
- Octal to Binary Encoder
- Hexadecimal to Binary Encoder
- Priority Encoder

Among all the above-given encoders. The priority encoders were developed to overcome the disadvantages associated with other 3 encoders. Here, we will see why priority encoders show an advantage over normal binary encoders.

### Decimal to BCD Encoder

A decimal to BCD encoder has 10 input lines while 4 output lines. The 10 input lines correspond to decimal values and 4 output lines correspond to BCD code.

The figure below represents the decimal to BCD encoder:

Here, the 10 input lines from I_{0} to I_{9} shows the decimal input and Y_{0} to Y_{3} shows the BCD output.

The figure below shows the **truth table **for decimal to BCD encode

Input / Output | Y_{0} | Y_{1} | Y_{2} | Y_{3} |
---|---|---|---|---|

I_{0} | 0 | 0 | 0 | 0 |

I_{1} | 0 | 0 | 0 | 1 |

I_{2} | 0 | 0 | 1 | 0 |

I_{3} | 0 | 0 | 1 | 1 |

I_{4} | 0 | 1 | 0 | 0 |

I_{5} | 0 | 1 | 0 | 1 |

I_{6} | 0 | 1 | 1 | 0 |

I_{7} | 0 | 1 | 1 | 1 |

I_{8} | 1 | 0 | 0 | 0 |

I_{9} | 1 | 0 | 0 | 1 |

So, from the above table we can conclude that

**Y _{0} = I_{8} + I_{9}**

**Y _{1} = I_{4} + I_{5} + I_{6} + I_{7}**

**Y _{2} = I_{2} + I_{3} + I_{6} +I_{7}**

**Y _{3} = I_{1} + I_{3} + I_{5} + I_{7} + I_{9 }**

The figure below shows the logic circuit for decimal to BCD encoder:

### Octal to Binary Encoder

In octal to binary encoder 8 input and 3 output lines are present.

The applied input to the encoder corresponds to the octal values while the output shows the binary values.

The figure below represents octal to binary encoder:

Here, I_{0} to I_{7} represents the octal input and Y_{0} to Y_{2} shows the binary output values.

So, let us have a look at the** truth table** of octal to binary encoder:

Input / Output | Y_{0} | Y_{1} | Y_{2} |
---|---|---|---|

I_{0} | 0 | 0 | 0 |

I_{1} | 0 | 0 | 1 |

I_{2} | 0 | 1 | 0 |

I_{3} | 0 | 1 | 1 |

I_{4} | 1 | 0 | 0 |

I_{5} | 1 | 0 | 1 |

I_{6} | 1 | 1 | 0 |

I_{7} | 1 | 1 | 1 |

From the truth table, we can conclude that

**Y _{0} = I_{4} + I_{5} + I_{6} + I_{7}**

**Y _{1} = I_{2} + I_{3} + I_{6} + I_{7}**

**Y _{2} = I_{1} + I_{3} + I_{5} + I_{7}**

Hence the logic circuit will be given as:

### Hexadecimal to Binary Encoder

The hexadecimal to binary encoder contains 16 input lines as well as 4 output lines. So, the input provided shows the hexadecimal count and the output represents the binary values.

The figure shown below represents the hexadecimal to binary encoder:

Here, I_{0} to I_{F} represents the hexadecimal input and Y_{0} to Y_{3} represents binary output.

Let us have a look at the **truth table** of hexadecimal to binary encoder:

Input / Output | Y_{0} | Y_{1} | Y_{2} | Y_{3} |
---|---|---|---|---|

I_{0} | 0 | 0 | 0 | 0 |

I_{1} | 0 | 0 | 0 | 1 |

I_{2} | 0 | 0 | 1 | 0 |

I_{3} | 0 | 0 | 1 | 1 |

I_{4} | 0 | 1 | 0 | 0 |

I_{5} | 0 | 1 | 0 | 1 |

I_{6} | 0 | 1 | 1 | 0 |

I_{7} | 0 | 1 | 1 | 1 |

I_{8} | 1 | 0 | 0 | 0 |

I_{9} | 1 | 0 | 0 | 1 |

I_{A} | 1 | 0 | 1 | 0 |

I_{B} | 1 | 0 | 1 | 1 |

I_{C} | 1 | 1 | 0 | 0 |

I_{D} | 1 | 1 | 0 | 1 |

I_{E} | 1 | 1 | 1 | 0 |

I_{F} | 1 | 1 | 1 | 1 |

Thus we can conclude from the above table:

**Y _{0} = I_{8} + I_{9} + I_{A} + I_{B }+ I_{C} + I_{D} + I_{E} + I_{F}**

**Y _{1} = I_{4} + I_{5} + I_{6} + I_{7 }+ I_{C} + I_{D} + I_{E} + I_{F}**

**Y _{2} = I_{2} + I_{3} + I_{6} + I_{7 }+ I_{A} + I_{B} + I_{E} + I_{F}**

**Y _{3} = I_{1} + I_{3} + I_{5} + I_{7 }+ I_{9} + I_{B} + I_{D} + I_{F}**

So, the logic circuit will be given as

### Priority Encoder

Priority encoders are a special type of encoders that were developed to eliminate the drawback associated with normal encoders.

As when multiple inputs are high then the encoder will not be able to correctly respond to any one of the input. As in this case, an ambiguity will get generated.

Due to this, priority encoders were taken into consideration.

In priority encoders, with movement in downward direction, priority increases.

This means that the LSB will contain the lowest priority while the MSB has the highest priority.

Consider the 4:2 priority encoder shown below:

Here I_{0} to I_{3} represents the 4 input lines and Y_{0} and Y_{1} shows the output lines. Also, the priority encoder contains a 3^{rd} output line V which is termed as a valid bit.

This bit checks the availability of low signal at all the inputs. If all the 4 inputs are low, then at the output the valid bit will show 0 at the output.

So, we can say that at any point of time, if I_{3} will be high, then the circuit does not need to check any other input line. As among all the input data lines shown above, I_{3} holds the highest priority.

Thereby automatically the output will be generated according to the input I_{3}. So, in this way, the ambiguity of the generated result can be overcome by the priority encoders.

The truth table of 4:2 priority encoder is given below:

I_{0} | I_{1} | I_{2} | I_{3} | Y_{0} | Y_{1} | V |
---|---|---|---|---|---|---|

0 | 0 | 0 | 0 | * | * | 0 |

1 | 0 | 0 | 0 | 0 | 0 | 1 |

* | 1 | 0 | 0 | 0 | 1 | 1 |

* | * | 1 | 0 | 1 | 0 | 1 |

* | * | * | 1 | 1 | 1 | 1 |

**From the above-given truth table, we can conclude that**

When both the applied input is low then this shows the absence of valid input so, in this case, the output will be don’t care condition hence valid bit will set to 0.

Further when we see that input I_{0} is high then it is needed to check the state of I_{1}, I_{2} and I_{3}. As in this case, all the rest 3 inputs must be low. So, the output will be generated according to the input line I_{0}.

Proceeding further, when input I_{1} will be high then there exists no need to check the state of I_{0} as it holds the least priority. But, still the input lines I_{2} and I_{3} both has to be low. So output generated will be according to I_{1}.

In the same way, in the case of I_{2} only state of I_{3} is required to be checked. As it must be low to get the output according to I_{2}.

But when I_{3} goes high then rest 3 inputs falls in don’t care condition. As I_{3} has the highest priority and the output generated accordingly.

**So, it can be concluded that**

**Y _{0} = I_{2} + I_{3}**

**Y _{1} = I_{2} I^{I}_{1} + I_{3}**

**V = I _{0} + I_{1} + I_{2} + I_{3}**

The logic circuit is given as

So, this is all about binary encoders and its types.